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Very long instruction word
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11	EN164: Design of Computing Systems Lecture 20: Processor / ILP 1 Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Add to Reading List Source URL: scale.engin.brown.edu Language: English - Date: 2014-03-23 13:26:54 Parallel computing Classes of computers Central processing unit Superscalar Very long instruction word Hazard Instruction set Slot NOP Computer architecture Computing Computer engineering
12	Code Reordering and Speculation Support for Dynamic Optimization Systems Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu Center for Reliable and High-Performance Computing University of Illinois Urba Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:01 Out-of-order execution Electronics Very long instruction word Compiler optimization Instruction set Computer architecture Assembly languages Memory disambiguation Delay slot Computing Programming language implementation Explicitly parallel instruction computing
13	MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY A.I. Memo NoMay, 1994 Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:46 Parallel computing Automatic parallelization Microarchitecture Central processing unit Very long instruction word Cell Supercomputer Program optimization 64-bit Computing Concurrent computing Computer programming
14	MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY A.I. Technical Report NoJuly 1993 Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:06:06 Compiler optimizations Lisp programming language Parallel computing Programming language implementation Automatic parallelization Compiler Gerald Jay Sussman Very long instruction word Hal Abelson Computing Software engineering Computer programming
15	A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors Josep M. Codina, Jesús Sánchez and Antonio González Department of Computer Architecture Universitat Politècnica de Catalunya Barc Add to Reading List Source URL: research.ac.upc.edu Language: English - Date: 2002-03-20 08:48:01 Parallel computing Concurrent computing Central processing unit Instruction scheduling Very long instruction word Register allocation Computer cluster Processor register Thread Computing Computer architecture Compiler optimizations
16	The University of Hertfordshire The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures Jason McGuiness Add to Reading List Source URL: accu.org Language: English - Date: 2008-04-14 03:49:41 Central processing unit Parallel computing Classes of computers Microprocessors Instruction-level parallelism Superscalar Very long instruction word CPU cache Instruction set Computer architecture Computing Computer hardware
17	The University of Hertfordshire The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures Jason McGuiness Add to Reading List Source URL: www.accu.org Language: English - Date: 2008-04-14 03:49:41 Central processing unit Parallel computing Classes of computers Microprocessors Instruction-level parallelism Superscalar Very long instruction word CPU cache Instruction set Computer architecture Computing Computer hardware
18	MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARTIFICIAL INTELLIGENCE LABORATORY A.I. Memo NoApril 1993 Add to Reading List Source URL: repository.readscheme.org Language: English - Date: 2010-10-22 08:05:37 Computer architecture Compiler optimizations Microprocessors Very long instruction word Central processing unit Scheduling Software pipelining Stream processing Multi-core processor Computing Concurrent computing Parallel computing
19	This is the author’s version of the work. The definitive work was published in Proceedings of the Conference on Design, Automation and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014. Code Generation for Emb Add to Reading List Source URL: www12.informatik.uni-erlangen.de Language: English - Date: 2014-03-25 17:29:01 Graphics hardware OpenCL Graphics processing unit CUDA OpenCV Mali Very long instruction word Parallel computing Multi-core processor GPGPU Computing Computer hardware
20	In the Proceedings of the 35th International Symposium on Microarchitecture, Instabul, Turkey, NovemberVector Vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks Christoforos Kozyrakis Electr Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 2003-01-09 09:33:02 Parallel computing Classes of computers Central processing unit Instruction set architectures Superscalar Very long instruction word SIMD Microarchitecture Instruction set Computer architecture Computing Computer engineering

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